Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2017050038
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To suppress decrease in retention characteristics due to PVT variation.SOLUTION: A semiconductor memory 100 comprises: a memory cell array 100A composed of a plurality of SRAM cells 10 including an NMOS transistor and a PMOS transistor; and a bias circuit 100B connected to a ground GND1 or a power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes: NMOS transistors 121, 122, 133, 134 having the same channel length, the same channel width, and having the same dopant and dosage in a channel part, as those of the NMOS transistor in the SRAM cell 10; and PMOS transistors 111, 112 having the same channel length, the same channel width, and having the same dopant and dosage in a channel part, as those of the PMOS transistor in the SRAM cell 10. Diffusion regions of the NMOS transistor and the PMOS transistor are formed on the same semiconductor layer.SELECTED DRAWING: Figure 4
Inventors:
KAWASUMI ATSUSHI
Application Number:
JP2016034736A
Publication Date:
March 09, 2017
Filing Date:
February 25, 2016
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G11C11/413; H01L21/8244; H01L27/10; H01L27/11
Domestic Patent References:
| JPH10112188A | 1998-04-28 | |||
| JPS6066505A | 1985-04-16 | |||
| JP2007317346A | 2007-12-06 | |||
| JP2013525936A | 2013-06-20 |
Foreign References:
| US20120206953A1 | 2012-08-16 | |||
| US20120230126A1 | 2012-09-13 | |||
| US20110261609A1 | 2011-10-27 | |||
| US20060002223A1 | 2006-01-05 | |||
| US20150170736A1 | 2015-06-18 |
Attorney, Agent or Firm:
Sakai International Patent Office
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