Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3135678
Kind Code:
B2
Abstract:
PURPOSE: To prevent the reading of erroneous data, and to attain a high speed access even when a reset is operated during a serial access by adding a transfer gate and a data latch.
CONSTITUTION: The data of the (a) sector of each line are transferred and held through a second transfer gates 155-157 to a second data latch 134-136 by rising a second transfer signal T2. Then, when the reset is operated to each line, and a reading operation is moved to the next line, the data of the (a) sector of each line can be transferred from the second data latch 134-136 through a third transfer gates 158-160 to a first data latch 137-139 by rising a third transfer signal T3 in a cycle next to the reset.
Inventors:
Masanori Hirose
Minoru Hatta
Masaru Fujii
Naoto Kii
Minoru Hatta
Masaru Fujii
Naoto Kii
Application Number:
JP14962692A
Publication Date:
February 19, 2001
Filing Date:
June 09, 1992
Export Citation:
Assignee:
Matsushita Electronics Industrial Co., Ltd.
International Classes:
G11C11/401; H04N5/907; (IPC1-7): G11C11/401; H04N5/907
Domestic Patent References:
| JP63311697A | ||||
| JP63220496A | ||||
| JP6496896A |
Attorney, Agent or Firm:
Akio Miyai
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