Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3225505
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent an erroneous sensing operation when a semiconductor memory is read out and to operate the semiconductor memory at higher speed.
SOLUTION: After an active command ACTCMD is activated, a readout command RCMD is activated. The active command ACTCMD is input to a column address latch circuit 30. On the basis of the output of the column address latch circuit 30 and on the basis of the output of a driver control circuit 70, a left driver 50 and a right driver 51 are driven. Either a memory cell array 10 or a memory cell array 11 is selected. The readout command ECMD is input to a row address latch circuit 20. The output of the row address latch circuit 20 is input to a row decoder 21. A row selection signal YSW which selects the row of the memory cell arrays 10, 11 is generated by the output of the row decoder 21. After the readout command RCMD is inactivated, the row selection signal YSW is sent out from the row decoder 21, and a memory cell is read out.
Inventors:
Yoshifumi Mochida
Application Number:
JP21300498A
Publication Date:
November 05, 2001
Filing Date:
July 28, 1998
Export Citation:
Assignee:
NEC
International Classes:
G11C11/401; G11C11/407; G11C11/409; G11C16/02; (IPC1-7): G11C11/409; G11C11/407; G11C16/02
Domestic Patent References:
| JP9288888A |
Attorney, Agent or Firm:
Johei Yamashita