Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3289701
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor memory which can be performed with high speed operation by dissolving deterioration of an operational characteristic caused by difference of arrival time from each storage region of read-out data to an output circuit and reducing a delay element until read-out data output.
SOLUTION: Input serial data including data of one bit at the points of respective time of rise and fall of a basic clock are divided into even data at the time of rise of an external basic clock and odd data at the time of fall by a demultiplexer DE-MUX, and they are written in memory cell arrays SAe, SAo respectively. A storage section of even data in which data of a bit read out first are included such as the memory cell array SAe and the like is arranged to a side closing to an input/output pad PA, at the time of read-out, the first read-out data are transmitted always to the multiplexer MUX through a shorter wiring from a parallel-serial conversion circuit.
Inventors:
Sachiko Edo
Application Number:
JP10462299A
Publication Date:
June 10, 2002
Filing Date:
April 12, 1999
Export Citation:
Assignee:
NEC
International Classes:
G11C11/413; G11C7/10; G11C11/401; G11C11/407; G11C11/41; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/407; G11C11/401; G11C11/413; H01L27/10
Domestic Patent References:
| JP2000188381A | ||||
| JP4149889A |
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)