Title:
半導体メモリ
Document Type and Number:
Japanese Patent JP4127711
Kind Code:
B2
Abstract:
A semiconductor memory device includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in the second wiring region include a second portion, a second lead portion and a second inclined portion. The first and second portions are located in parallel with a same pitch, the first and second lead portions are located with a pitch which is larger than the pitch of the first and second portions, the first and second inclined portions extend the same direction at a predetermined angle.
Inventors:
Kazuo Saito
Application Number:
JP2006151539A
Publication Date:
July 30, 2008
Filing Date:
May 31, 2006
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/8247; G03F1/00; G03F1/70; H01L21/3205; H01L21/336; H01L21/768; H01L23/52; H01L23/522; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2000076880A | ||||
| JP2000022895A |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto