Title:
半導体メモリ
Document Type and Number:
Japanese Patent JP6738711
Kind Code:
B2
Abstract:
A semiconductor memory includes j×k first memory cells, j upper bit lines, (½)j sense amplifiers, j×k lower first bit lines, k first word lines, k pairs of plate lines, each pair having first and second plate lines, each being connected to odd-numbered and even-numbered first memory cells of one of the k columns, a pair of discharge signal lines having a first discharge signal line and a second discharge signal line respectively connecting two of the j upper lines in each sense amplifier to a prescribed potential, j×m second memory cells, j lower second bit lines, m second word lines, m third plate lines each connected to the j second memory cells of one of the m columns, and j shield lines each provided at positions respectively corresponding to the j upper bit lines, which are parallel to one another.
Inventors:
Kazushi Yamada
Application Number:
JP2016212082A
Publication Date:
August 12, 2020
Filing Date:
October 28, 2016
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
G11C11/22; G11C7/18
Domestic Patent References:
| JP2005209324A | ||||
| JP201160342A |
Attorney, Agent or Firm:
Motohiko Fujimura
Shinji Takano
Shinji Takano