PURPOSE: To shorten the propagation delay time of a signal and to accelerate access time by uniformalizing the length of an input/output signal line to which a memory cell array block is connected.

CONSTITUTION: Such layout that memory cell arrays 1a-4b in which memory cells are arranged in matrix shape are divided into plural blocks and peripheral blocks are connected by plural input/output signal lines 6-9 is employed. Each memory cell block is arranged in such a way that the memory cell blocks neighbored to the peripheral blocks 5, 11 of each memory cell array block are connected to remote memory blocks so as to uniformalize the wiring length of the input/output signal lines 6-9 connected to the memory cell array blocks 1a-4b, respectively.