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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH0432095
Kind Code:
A
Abstract:

PURPOSE: To completely execute the amplification and to output a sufficient potential level to an external output signal line by delaying a conduction time of a transfer gate in accordance with a fact that a potential difference amplified by a differential amplifying circuit becomes small.

CONSTITUTION: The semiconductor memory is provided with a circuit for delaying a conduction time of transfer gates TA, TB in accordance with a fact that a potential difference amplified by a differential amplifying circuit 1 becomes small. In the case levels of nodal points M, N do not reach a power source level and a GND level, respectively, the current capacity of transfer gates TY1, TY2 becomes small, therefore, it is delayed by that portion that the transfer gates TA, TB become a conducting state. Even if an operation delay of a sense amplifier is generated, the transfer gates TA, TB conduct after a potential difference of a pair of digit lines D, the inverse of D is amplified enough, and a sufficient potential level can be given to external output signal lines I01, I02. In such a way, a sufficient potential level can be given to the external output signal line.


Inventors:
NAKAYAMA HIROSHI
Application Number:
JP13737490A
Publication Date:
February 04, 1992
Filing Date:
May 28, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C7/10; G11C11/407; G11C11/409; G11C11/419; (IPC1-7): G11C11/409; G11C11/419
Attorney, Agent or Firm:
Seiichi Kuwai



 
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