PURPOSE: To attain data update without stopping a processor by providing a control circuit for miss hit, activating an input data control part and holding data provided for the processor.

CONSTITUTION: At the time of generating a miss hit, the control circuit part 10 for miss hit is operated by control signals CS, OE and WE outputted from a control part so as to generate an output signal making the input data control part 4 into an active state and an output signal making an output data control part 7, a sense switch 5 and a control system circuit part 9 into an inactive state. By the output signals, the output data control part 7, the sense switch 5 and the control system circuit part 9 are made into the inactive state and the input data control part 4 is made into the active state to be in a writing possible state. Then, address buffers 1 and 8 and decoders 2 and 6 are operated to select one or plural cells in a memory cell array.