PURPOSE: To obtain a semiconductor memory which can shorten a test time.

CONSTITUTION: A memory cell array 2 consisting of plural memory cells is provided in a DRAM 1, and the memory cells are selected by an address decoder 3 based on an external address signal. When the memory cells of the memory cell array 2 are tested, a converter circuit 4 converts a physical address for a normal mode which selects one memory cell from the outside and tests it to a physical address for a test mode which selects plural memory cells and tests it, and output it. A switching signal generation circuit 5 generates a switching signal CH based on a control signal externally inputted and outputs it. A switching circuit 6 inputs the physical address for a normal mode and the physical address for a test mode from the converter circuit 4, switches the physical address for a normal mode with the physical address for a test mode, and outputs it to the address decoder 3 as an address signal.