To efficiently relieve a defect by generating an ECC parity bit for storage data, storing them in a memory cell, relieving the defect in a bit cell with the error detection/correction of the data and preferably relieving the defect in the memory cell of the parity bit with a redundant circuit.
A memory array part is divided into 16 pieces of memory mats, and is constituted so as to be provided with capacity of nearly 64 M bits in all and to input/output the data in 137 bits. An ECC circuit is arranged between the memory array part and an input/output part, and the parity bit of an expansion humming code consisting of 9 bits is generated to be stored in 137 pieces of memory cells. A piece of memory mat is provided with reserve sub-word lines by four pieces much and reserve bit line pairs by two circuits much for relieving the defect, and the defect is relieved preferably for a complementary bit line for the parity bit and the memory cell of the parity bit.
NAKAI KIYOSHI
IWAI HIDETOSHI
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