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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS54114086
Kind Code:
A
Abstract:

PURPOSE: To simplify the peripheral circuit for driving by forming the MOS capacitor with installatin of the fixed bias applying conducting layer via the insulator film on the charge storage region corresponding to the drain region of the electrostatic inducting transistor and then using the gate and source regions for the word and bit wires respectively.

CONSTITUTION: Exclusive bit N+-buried layer is formed through diffusion on P--type Si substrate 12 to be used as the source region, and then N--type layer 14 is epitaxial-grown on the entire surface. Layer 14 is isolated into the island-shaped regions via P-type region 18, and P+-type gate region 20 which is to be the word wire is formed through diffusion and with a distance between within island-shaped region 14A. Thus, charge storage region 22 corresponding to the drain region is grown at the region surrounded by region 20 and not connected to any electrode to be put under the floating state. After this, protective film 26 including SiO2 film 24 on region 22 is coated on the entire surface, and fixed bias voltage applying poly-crystal Si layer 28 is coated over film 24 through 26 with attachment of word conductor layer 30 to region 22.


Inventors:
NISHIZAWA JIYUNICHI
MOCHIDA YASUNORI
NONAKA TERUMOTO
Application Number:
JP2133478A
Publication Date:
September 05, 1979
Filing Date:
February 25, 1978
Export Citation:
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Assignee:
NIPPON MUSICAL INSTRUMENTS MFG
International Classes:
G11C11/41; H01L27/10; H01L27/108; H01L29/78; (IPC1-7): G11C11/40; H01L27/10; H01L29/76