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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS5710283
Kind Code:
A
Abstract:
The semiconductor memory contains a degenerate semiconductor layer (1) and a nondegenerate semiconductor layer (2) having traps in the energy gap. The conductivity type of the degenerate semiconductor layer (1) is opposite to that of the nondegenerate semiconductor layer (2). Situated between the degenerate semiconductor layer (1) and the nondegenerate semiconductor layer (2) is a dielectric layer (4) capable of tunnel conduction. Deposited on the nondegenerate semiconductor layer (2) is a layer of material (5) which forms a potential barrier with the nondegenerate semiconductor layer (2) and, together with the dielectric layer (4) which is capable of tunnel conduction, prevents the penetration of the charge carriers from the degenerate semiconductor layer (1) and from the ohmic contact (6) into the nondegenerate semiconductor layer (2).

Inventors:
MORUDEYUKU IRITSUCHI ERINSON
MARATO RAIMUDOZANOBUITSUCHI MA
BORISU AREKUSEEBUITSUCHI MARAH
BUADEIMU IWANOBUITSUCHI POKARU
SERUGEI ANATORIEBUITSUCHI TERE
GENRIKU URADEIMIROBUITSUCHI SU
BUITARII GEORUGIEBUITSUCHI TES
Application Number:
JP7337081A
Publication Date:
January 19, 1982
Filing Date:
May 15, 1981
Export Citation:
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Assignee:
OORUDENA TOURUDOOBOBO KURASUNO
International Classes:
G11C16/02; G11C17/00; H01L21/8246; H01L27/112; H01L21/8247; H01L29/15; H01L29/74; H01L29/788; H01L29/792; H01L29/861; H01L45/00; (IPC1-7): G11C11/34; H01L29/66; H01L45/00



 
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