Title:
SEMICONDUCTOR MOS INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2005236654
Kind Code:
A
Abstract:
To lower operating voltage, without increasing power consumption in a sleep state, in particular, about a semiconductor MOS integrated circuit with a switch installed between a digital circuit and a power source.
Operating voltage can be lowered, without being blocked by threshold voltages of high threshold MOSFETs that have been a factor which blocks the voltage reduction of power supply voltage, because of being provided with independent power sources 8 and 9 for applying a voltage which ich higher than the thresholds of the high threshold MOSFETs for power switches (Q1 and Q2) between the gates and the sources of the MOSFETs.
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Inventors:
SHIBATA SHINTARO
Application Number:
JP2004043163A
Publication Date:
September 02, 2005
Filing Date:
February 19, 2004
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03K17/06; H03K17/30; H03K17/687; H03K19/00; H03K19/0948; (IPC1-7): H03K19/00; H03K17/06; H03K17/30; H03K17/687; H03K19/0948
Attorney, Agent or Firm:
Hidekazu Miyoshi