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Title:
SEMICONDUCTOR NONVOLATILE MEMORY CELL
Document Type and Number:
Japanese Patent JPS62159472
Kind Code:
A
Abstract:

PURPOSE: To flatten and microminiaturize a semiconductor nonvolatile memory cell by burying a first layer gate insulating film and a floating gate between a source region and a drain region on a semiconductor substrate.

CONSTITUTION: After an oxide film 301 is formed on an Si substrate, a trench structure is formed on a portion to become a gate. Then, the film 301 is re moved, and a side wall 302 is formed by a nitride film. Then, after an oxide film 303 is formed on the overall surface, the wall 302 is separated, and a thin oxide film 304 is further formed. Subsequently, a polysilicon is deposited, and etched to the surface of the substrate to form a floating gate 305. After an oxide film 306 is formed on the entire surface, a control gate 307 is formed, a drain region 308 and a source region 309 are ion implanted to obtain a nonvolatile memory cell. Thus, the cell can be flattened and microminiaturized.


Inventors:
SHIBAZAKI MASAHIKO
Application Number:
JP99286A
Publication Date:
July 15, 1987
Filing Date:
January 07, 1986
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H01L21/8247; H01L29/78; H01L29/788; H01L29/792; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
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