To lessen the circuit area of a decoder of a word line drive system circuit and to make high the charging-discharging speed of a word line at the time of erase/write/verification, by controlling a transfer gate to be in a state of continuity in a read operation mode and to be in a state of non-continuity in an erase or write operation mode.

A read system decoder circuit 30 supplies a transfer gate 60 with a word line drive voltage at a read time. An erase/write system decoder circuit 40a outputs a positive or negative high voltage PV, MV in an erase/write/verification mode and supplies a word line WL with a drive voltage of the same value as the word line drive voltage for read at the read time. The transfer gate 60 is controlled to be in a state of continuity in a read mode and to be in a state of non-continuity in the erase/write/verification mode by a transfer gate control circuit 50a.