SEMICONDUCTOR PACKAGE HAVING OFFSET DIE PAD AND ITS MANUFACTURE

Title:

SEMICONDUCTOR PACKAGE HAVING OFFSET DIE PAD AND ITS MANUFACTURE

Document Type and Number:

Japanese Patent JPH10256455

Kind Code:

A

Abstract:

To provide a semiconductor package having offset die pads and a method for manufacturing the package.

A semiconductor package 64 contains stiffener strips 10 having die pads 18 and body sections 12. The first surface of each die pad 18 is offset from the second surface of each body section 12 by a prescribed amount. Each stiffener strip 10 contains an inner edge 27 which is concentrically positioned to the periphery of the pad 18 and a tie strap 16 which connects the inner edge 27 to the die pad 18. A die 28 is attached to the first surface of the die pad 18. A substrate 20 has first and second surfaces and the second surface is attached to the first surface of the body section 12. The substrate 20 contains a window and conductive elements. A plastic molding material covers at least parts of the die 38, stiffener strip 10, and substrate 20.

Inventors:

HASSANTADEH NOZAR
JARMAN HALL E
STEARNS WILLIAM P

Application Number:

JP919198A

Publication Date:

September 25, 1998

Filing Date:

January 21, 1998

Export Citation:

Click for automatic bibliography generation Help

Assignee:

TEXAS INSTRUMENTS INC

International Classes:

H01L21/56; H01L23/495; H01L23/50; (IPC1-7): H01L23/50; H01L21/56

Attorney, Agent or Firm:

Minoru Nakamura (6 outside)

Previous Patent: LEAD FRAME AND ITS MANUFACTURE

Next Patent: METHOD FOR DESIGNING LEAD FRAME TIP LAYOUT