Title:
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3676646
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor package and its manufacturing method for preventing an electrical short circuit.
SOLUTION: A BGA package 300 includes a semiconductor chip 210, a substrate 220, a bonding wire 250 for electrically connecting a pad 212 of the semiconductor chip 210 to the substrate 220. A manufacturing step includes a step for forming a semiconductor wafer, made up of an integrated circuit with a plurality of semiconductor chips on an active face of the silicon substrate, a plurality of pads electrically connected to the integrated circuit, an inactive layer formed on active faces other than the pads, and a polyimide layer formed on the inactive layer and extending to a scribe region, a step for removing the polyimide layer other than that of the scribe region from the pad, a step for cutting the semiconductor wafer along the scribe region and separating into pieces of semiconductor chips, a step for mounting the semiconductor chip on the substrate, and a step for electrically connecting the pad of the semiconductor chip to the substrate by wire bonding.
Inventors:
Chung Life Mouth
Choi
Lee Soo Tue
Choi
Lee Soo Tue
Application Number:
JP2000132409A
Publication Date:
July 27, 2005
Filing Date:
May 01, 2000
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/60; H01L21/78; H01L23/31; H01L21/304; (IPC1-7): H01L21/60
Domestic Patent References:
| JP11135539A | ||||
| JP4305945A | ||||
| JP60064442A | ||||
| JP62042533A | ||||
| JP8124957A | ||||
| JP62043137A | ||||
| JP61241959A | ||||
| JP11031756A | ||||
| JP4162638A | ||||
| JP4277637A | ||||
| JP11121507A |
Attorney, Agent or Firm:
Masaki Hattori
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