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Title:
SEMICONDUCTOR PATTERN POSITIONING METHOD, AND SUBSTRATE WAFER FOR USE THEREIN
Document Type and Number:
Japanese Patent JP2005183562
Kind Code:
A
Abstract:

To position front and rear circuit patterns of a semiconductor substrate including high-density circuit patterns formed by exposure on front and rear surfaces of a substrate wafer.

Long grooves 3a, 3b and 4a, 4b, extending along the x-axis and the y-axis orthogonal to each other and originating at the origin 0 set on the substrate wafer 2 are formed in advance on the front surface 2a and the rear surface 2b of the substrate wafer 2. Markers 5a, 5b and 6a, 6b, formed corresponding to the photomasks 5 and 6 for exposure-formation of circuit patterns 7a and 7b by an exposure apparatus 1 on the surfaces 2a and 2b, are aligned with the grooves 3a and 3b on the wafer front surface 2a and grooves 4a and 4b on the wafer rear surface 2b of the substrate wafer 2. Exposure is performed by the exposure apparatus 1 for the transfer and the formation of the front-surface pattern 7a and the rear-surface pattern 7b for the thin-film circuit substrate 7 for manufacturing the semiconductor device.


Inventors:
YAMAGUCHI HIDEKI
Application Number:
JP2003420321A
Publication Date:
July 07, 2005
Filing Date:
December 18, 2003
Export Citation:
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Assignee:
NEC CORP
International Classes:
G03F9/00; H01L21/027; (IPC1-7): H01L21/027; G03F9/00
Attorney, Agent or Firm:
Masahiro Fukuyama