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Patent Searching and Data


Title:
SEMICONDUCTOR RESISTANCE DEVICE
Document Type and Number:
Japanese Patent JPS6412568
Kind Code:
A
Abstract:

PURPOSE: To decrease the effect based on the change of bias voltage by a method wherein an opposite conductivity type resistive layer facing a semiconductor substrate is composed of a region low in impurity concentration adjacent to the semiconductor substrate and another region which is high in impurity concentration and provided above the former.

CONSTITUTION: An n-type layer 2 is formed on a p-type substrate 1. The layer 2 is isolated through a p+ isolating region 3 as it is made to be island-shaped. A p-type resistive layer 4 low in impurity concentration is laid on the layer 2. The layer 4 is composed of two regions which are a comparatively high concentrated region 42 that makes a contribution to the resistance value and a p- region 42 that is equal to or lower in concentration than the layer 2 and provided under the region 42. The layer 4 functions as a resistor against the voltage impressed through electrodes 5 and 6. Inverted bias voltage is impressed on the layer 2 through an ohmic junction 7 so as to make the layer 2 higher in potential than the substrate 1. In this structure, the change of the layer in carrier concentration to that of the inverted bias voltage is made to be decreased, and consequently the resistance value can be kept stable.


Inventors:
HANIWARA KOJI
Application Number:
JP16783287A
Publication Date:
January 17, 1989
Filing Date:
July 07, 1987
Export Citation:
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Assignee:
PIONEER ELECTRONIC CORP
PIONEER VIDEO CORP
International Classes:
H01L27/04; H01L21/822; H01L27/08; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Hideo Takino