PURPOSE: To speed up access by serially outputting data being parallel selected in a byte unit by an address signal to be generated by a clock signal being inputted from an outside.

CONSTITUTION: A counter 1 to generate the address signal with a clock signal 2 being inputted from the outside and a shift register 8 to serially convert and output the data being parallel selected in the byte unit by the address signal are provided. The data being latched by the shift register 8 are serially outputted from the clock signal 2 at timing with a specific delay, simultaneously the address counter is counted up only by one and a next address is sent out to a memory cell. During that time, the data of the cell being previously selected from a shift register 8 are serially outputted to an outside data bus 9. Thus, high speed operation can be executed when the data are successively transferred.