Title:
半導体記憶装置、半導体記憶装置の制御方法、そのプログラム及び半導体記憶装置の製造方法
Document Type and Number:
Japanese Patent JP6808668
Kind Code:
B2
Abstract:
A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.
Inventors:
Ashihiro Ushiryu
Akira Kano
Kenji Hirohata
Akira Kano
Kenji Hirohata
Application Number:
JP2018045486A
Publication Date:
January 06, 2021
Filing Date:
March 13, 2018
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/8239; H01L27/105; H01L45/00; H01L49/00
Domestic Patent References:
| JP2005197634A | ||||
| JP2017191918A | ||||
| JP2018007219A |
Other References:
岡田葵 他,4H-Sic PIN diodeにおける積層欠陥の拡張/縮小現象に温度・電流密度が及ぼす影響,先進パワー半導体分科会 第3回講演会,2016年11月 8日,pp. 138-139
Attorney, Agent or Firm:
Sakai International Patent Office