To generate an electric field in the section of a silicon board opposed to a charge storage section by capacity junction while obtaining a sufficient channel current by lowering a threshold voltage of the section of the silicon board.

A semiconductor storage device is configured of a semiconductor board 21 forming a trapezoidal step 21b, a first well 32, a gate electrode 38 fitted on the step through a gate oxide film 36, an impurity diffusion region 28, second wells 34a and 34b and the charge storage section 40. The first well is formed in a first conductivity type region formed in the surface layer region of the top face of the step section. The second wells are formed in the first conductivity type region formed extensively over the surface layer region of the side face of the step from a region adjacent to the impurity diffusion region of a flat region between the first well and the impurity diffusion region and having an impurity concentration lower than that of the first well. The charge storage section is constituted by successively laminating a bottom oxide film 42a, a charge storage film 44a, a top oxide film 46a and a floating electrode 48a at places sandwiching a control electrode.