To provide a self repair method using a redundancy line determination method in which a hardware process is conducted for a final repair address on a chip employing a small circuit scale based on the result of a storage means.

A BIST circuit 20 which evaluates normal/defective condition of an individual cell, a buffer 31 which stores address information of abnormal cells transmitted from the circuit 20 and a RAM10 are mounted on a same chip. Absolute minimum address information that is used to determine a redundancy cell to be replaced, among the address information of abnormal cells transmitted by the circuit 20 is determined by a repair search circuit 30 and only the determined address information is stored into the buffer 31. A final repair address is computed by hardware on the chip for the case of a zero-order redundancy constitution based on the stored address information to conduct self repair. Thus, problems in which testing becomes difficult using an external tester for a memory having redundancy lines where LSI is complex and memory testing to be conducted in an actual speed is difficult due to the increase in the memory speed, are eliminated.

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