PURPOSE: To furnish a semiconductor memory having a self-amplification type memory cell structure being easy to make minute and executing a stable cell operation.
CONSTITUTION: WM for writing and RM for reading are made MOS transistors of P and N channels. A floating gate of the RM is connected to a bit line DL through a source-drain route of the WM, while a source-drain route of the RM is connected between the bit line DL and a prescribed potential point Vss, and the gate of the RM and a gate of the WM are connected to a word line WL. When the word line WL is set at a low potential, according to this constitution, the WM turns ON, information from the bit line DL is stored in the floating gate of the RM and a threshold voltage of the RM is set. When the word line WL is set at a high potential, the RM turns ON or OFF in accordance with a threshold value and reading can be executed. A cell can be constructed of one bit line, and therefore one word line and the area of the cell can be reduced remarkably.
KAGA TORU
KIMURA SHINICHIRO
HISAMOTO MASARU
SAGARA KAZUHIKO
KURE TOKUO
TAKEDA EIJI
