Title:
半導体記憶装置及び半導体装置の製造方法
Document Type and Number:
Japanese Patent JP6437351
Kind Code:
B2
Abstract:
According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.
Inventors:
Sakuma Research
Shosuke Fujii
Masumi Saito
Toshiyuki Sasaki
Shosuke Fujii
Masumi Saito
Toshiyuki Sasaki
Application Number:
JP2015050524A
Publication Date:
December 12, 2018
Filing Date:
March 13, 2015
Export Citation:
Assignee:
Toshiba Memory Corporation
International Classes:
H01L21/8239; H01L27/105; H01L45/00; H01L49/00
Domestic Patent References:
| JP2014150236A | ||||
| JP2014057067A | ||||
| JP2007201454A |
Foreign References:
| US20140191178 | ||||
| WO2004021445A1 | ||||
| US20130308363 |
Attorney, Agent or Firm:
Kisaragi International Patent Business Corporation
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