To provide a memory system which relieves a system and also controls the reduction of memory capacity.

Respective SLDRAM(sink link dynamic random access memory) 5.0 to 5.n execute a test of an internal memory part in accordance with an execution command that is given from a memory controller 3 and give a defective address to the controller 3. The controller 3 stores the respective defective address of the SLDRAM 5.0 on 5.n and accesses only normal addresses without accessing the defective addresses. The decreasing rate of the memory capacity of a main memory 4 can be suppressed compared with the conventional practice in which an SLDRAM having defective addresses is not accessed.