To reduce a size of a memory cell array in an NOR flash memory having a two-transistor structure.
The NOR flash memory is composed so that a memory cell unit having a two-transistor structure is arrayed in a matrix shape, and a trench-type element isolation region isolates cell array rows. A mutual interval between a control gate electrode 14 of a cell transistor CT and a lower gate electrode 12a of a selection gate transistor ST adjacent to each other in a row direction in the memory cell unit MS is shorter than that of between the control gate electrodes 14 of the respective cell transistors, in the memory cell units of two lines adjacent to each other in the row direction, and that between upper gate electrodes 14a of the respective selection gate transistors in the memory cell units of two lines adjacent to each other in the row direction.
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
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