Title:
半導体記憶装置、半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP4885426
Kind Code:
B2
Abstract:
According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
Inventors:
Koji Kanamori
Teiichiro Nishisaka
Noriaki Kodama
Katayama Isao
Yoshihiro Matsuura
Kaoru Ishihara
Harada Yasushi
Tomonori Minenaga
Chihiro Oshita
Teiichiro Nishisaka
Noriaki Kodama
Katayama Isao
Yoshihiro Matsuura
Kaoru Ishihara
Harada Yasushi
Tomonori Minenaga
Chihiro Oshita
Application Number:
JP2004070537A
Publication Date:
February 29, 2012
Filing Date:
March 12, 2004
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L27/10; H01L21/322; H01L21/52; H01L21/58; H01L23/26; H01L23/58; H01L29/00; H01L23/31
Domestic Patent References:
| JP2005530A | ||||
| JP1215032A |
Attorney, Agent or Firm:
Shinji Hayami
Kana Nomoto
Satoshi Amagi
Kana Nomoto
Satoshi Amagi