SEMICONDUCTOR STORAGE DEVICE

Japanese Patent JP2004164769

A

To provide a small-scale semiconductor storage device which performs parallel/serial conversion of pre-fetched data at high speed.

Amplifier circuits (R/A) 111, 112, 121, 122 perform such ordering of a first stage that whether data is outputted in the first half (the first or the second) or it is outputted in the latter half (the third or the fourth) for data of four pairs of data bus based on a value of EZORG1 to which a value of a second bit from the least significant bit of a column address externally specified is reflected. Switch circuits 115, 135, 125, 145 perform such ordering of a second stage that which data is outputted first and which data is outputted second for two data outputted in the first half and which data is outputted third and which which data is outputted fourth for two data outputted in the latter half based on a value of EZORG0 to which a value of the least least significant bit of a column address externally specified is reflected.

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KONO TAKASHI

JP2002330982A

June 10, 2004

November 14, 2002

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RENESAS TECH CORP

G11C11/407; G11C7/10; G11C11/34; G11C11/40; G11C11/408; G11C11/409; G11C19/00; H01L27/148; (IPC1-7): G11C11/407; G11C11/409

Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai

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