To provide a semiconductor storage device for surely executing a set operation, a reset operation and a read operation with respect to a plurality of memory cells.
The semiconductor storage device includes: a memory cell array MA in which the memory cells MC configured of a series connection of diodes Di and variable resistors VR are arranged at crossing parts of a plurality of bit lines BL and a plurality of word lines WL; and a control circuit for alternatively driving the bit line BL and the word line WL. When a predetermined potential difference is applied to a selected memory cell MC arranged at the crossing parts of the bit line BL and the word line WL by the control circuit, the plurality of bit lines BL01:0 and BL81:0 to be alternatively driven at the same time by specifying by one address signal CA7 among a plurality of address signals CA0 to CA7 are dispersedly arranged within the memory cell array MA.
JP2005267837A | 2005-09-29 | |||
JP2004234707A | 2004-08-19 |
WO2008029446A1 | 2008-03-13 |
Kazuhiko Tamura