SEMICONDUCTOR STORAGE DEVICE

Japanese Patent JP2818571

B2

PROBLEM TO BE SOLVED: To prevent the generation of a data write error by defective voltage of a flash memory by newly providing a test region in a memory cell array, a write test circuit, a write-voltage detecting circuit, an output buffer circuit, etc.
SOLUTION: A write test circuit 13 generates a write test signal WTEST, and a write-voltage detecting circuit 18 generates a voltage detecting signal WREN when write voltage fed to a test region 142 in a memory cell array 14 reaches a reference value or less at the time of the execution of a write test. An output buffer circuit 15 changes over a mode to a test output mode in response to the supply of the write test signal WREST, and outputs write inhibit information to a CPU 2 as a test result in response to the supply of the voltage detecting signal WREN, and the CPU 2 stops write. Accordingly, since defective or nondefective write voltage can be judged before the execution of data write, data breakdown due to defective write voltage can be prevented.

Naotoshi Nakadai

JP3387996A

October 30, 1998

February 21, 1996

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Yamagata NEC Corporation

G11C16/02; G11C16/22; G11C29/00; G11C29/24; G01R31/28; G11C29/46; (IPC1-7): G11C29/00; G01R31/28; G11C16/02

Naoki Kyomoto (2 outside)

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