Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JP2929847
Kind Code:
B2
Abstract:
PURPOSE: To increase the quantity of stored electric charge in the capacitor of a memory cell without increasing the occupation area of the memory cell.
CONSTITUTION: Bit lines BL and BR are divided into plural sections, and memory cells MC1 and MC3 connected to each section consist of transistors QC1 and capacitors CS1. When a word line &phiv W is selected after the completion of pre-charging of a balancer B1, a node N1 of the memory cell MC1 is connected to the bit line BL. The capacitor CS1 is connected to a control signal line &phiv S1 and has a potential different from a fixed potential VH, and thereby, the quantity of stored electric charge in the capacitor CS1 is increased before the next access.
Inventors:
KOMURO TOSHIO
Application Number:
JP19639092A
Publication Date:
August 03, 1999
Filing Date:
June 30, 1992
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G11C11/404; G11C11/402; G11C11/409; (IPC1-7): G11C11/404
Domestic Patent References:
| JP492285A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)