Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP3559732
Kind Code:
B2
Abstract:
A semiconductor memory apparatus, includes a current detecting circuit (1-1), an input signal generating circuit (2-1), a reference current detecting circuit (1R), a reference input signal generating circuit (2R) and a differential amplifier circuit (SEN-1). The current detecting circuit (1-1) detects a current (IS1) flowing through a memory cell (M1) to output a detecting signal (VS1) from an output section of the current detecting circuit (1-1). The input signal generating circuit (2-1) generates a first differential input signal (VSE1) obtained by amplifying the detecting signal (VS1) to output from an output section of the input signal generating circuit (2-1). The reference current detecting circuit (1R) detects a current (IR) flowing through a reference cell (MR) to output a reference detecting signal (VR) from an output section of the reference current detecting circuit (1R). The reference input signal generating circuit (2R) generates a second differential input signal (VRE) obtained by amplifying the reference detecting signal (VR) to output from an output section of the reference input signal generating circuit (2R). The differential amplifier circuit (SEN-1) detects a voltage difference between the first and second differential input signals (VSE1, VRE).
Inventors:
Masayoshi Hirata
Application Number:
JP25139999A
Publication Date:
September 02, 2004
Filing Date:
September 06, 1999
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
G11C16/06; G11C7/06; G11C7/14; G11C16/02; G11C16/28; (IPC1-7): G11C16/06; G11C16/02
Domestic Patent References:
| JP7029385A | ||||
| JP5136361A | ||||
| JP8255495A |
Attorney, Agent or Firm:
Tatsuo Tokumaru