Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JP3792602
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of performing a tRCD test adapted to the reduction in time between command inputs even when the test employs a memory testing apparatus inoperable for a high speed clock.
SOLUTION: The semiconductor storage device is configured to include: a command decoder for respectively producing control signals corresponding to entered commands when receiving a plurality of kinds of the commands to set an ordinary operating mode; and a row address pre-latch circuit for storing a row address except a bank address received together with a precharge command when the semiconductor storage device is set to a test mode and outputting the row address to a row address latch circuit. The row address latch circuit holds a row address outputted from the row address prelatch circuit synchronously with a control signal generated by an input of an active command, and a column address latch circuit holds a column address having been already received at the input of the active command synchronously with a control signal produced by the input of either of a read command and a write command.
Inventors:
Shigeyuki Nakazawa
Application Number:
JP2002155854A
Publication Date:
July 05, 2006
Filing Date:
May 29, 2002
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
G01R31/28; G01R31/319; G11C29/56; G11C8/06; G11C11/401; G11C11/407; G11C29/12; G11C29/18; (IPC1-7): G11C29/00; G01R31/28; G01R31/319; G11C11/401
Domestic Patent References:
| JP11312397A | ||||
| JP11144497A | ||||
| JP11317098A | ||||
| JP2000207900A | ||||
| JP2002352597A |
Attorney, Agent or Firm:
Akio Miyazaki
Masaaki Ogata
Ishibashi Masayuki
Masaaki Ogata
Ishibashi Masayuki