Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4028499
Kind Code:
B2
Abstract:
A semiconductor storage device includes a semiconductor substrate; an sulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, the memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of the memory cells aligned in the channel lengthwise direction; and a memory cell array including a plurality of the memory cell lines aligned in a channel widthwise direction of the memory cells.
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Inventors:
Takashi Osawa
Application Number:
JP2004056298A
Publication Date:
December 26, 2007
Filing Date:
March 01, 2004
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/762; H01L21/8242; G11C11/401; H01L21/76; H01L27/10; H01L27/108; H01L27/12; H01L31/119
Domestic Patent References:
| JP2010867A | ||||
| JP5235299A | ||||
| JP2002246571A | ||||
| JP2003258125A | ||||
| JP2003007856A |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Akaoka Akira
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Akaoka Akira