Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4262911
Kind Code:
B2
Abstract:
A semiconductor memory device has a dummy bit line, a reference voltage generating circuit, a comparator circuit, and a timing signal generating circuit. The dummy bit line has a load equal to a load of a bit line, and the reference voltage generating circuit generates a reference voltage. The comparator circuit compares a potential of the dummy bit line with the reference voltage, and the timing signal generating circuit generates various kinds of timing signals based on an output of the comparator circuit. The semiconductor memory device simultaneously selects a plurality of dummy memory cells and connects the selected dummy memory cells to the dummy bit line, and adjusts the potential of the dummy bit line.
Inventors:
Wataru Yokozeki
Application Number:
JP2001296678A
Publication Date:
May 13, 2009
Filing Date:
September 27, 2001
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G11C11/401; G11C11/4099; G11C7/12; G11C7/14; G11C11/4076; G11C11/409; G11C11/4091; G11C11/4094; G11C11/417; G11C17/00
Domestic Patent References:
| JP11339476A | ||||
| JP9259589A | ||||
| JP9270195A | ||||
| JP11265586A | ||||
| JP7147087A |
Attorney, Agent or Firm:
Atsushi Aoki
Koichi Itsubo
Higuchi Souji
Masami Enohara
Kurachi Yasuyuki
Ryu Kobayashi
Koichi Itsubo
Higuchi Souji
Masami Enohara
Kurachi Yasuyuki
Ryu Kobayashi