Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4768256
Kind Code:
B2
Abstract:
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.
Inventors:
Noboru Shibata
Application Number:
JP2004364902A
Publication Date:
September 07, 2011
Filing Date:
December 16, 2004
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C16/06; G11C16/02; G11C16/04; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2004185688A | ||||
| JP11045986A |
Attorney, Agent or Firm:
Hiroshi Horiguchi