Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP6457792
Kind Code:
B2
Abstract:
A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation. The first writing operation is a writing operation for applying a first voltage of a first polarity to the memory cell. The second writing operation is a writing operation for applying a second voltage of a second polarity opposite to the first polarity to the memory cell. The rewriting operation is a writing operation for, when the first writing operation fails, further executing a second A writing operation for applying the second voltage of the second polarity to the memory cell and a first A writing operation for applying the first voltage of the first polarity to the memory cell.
Inventors:
Kiyoshi Takeuchi
Akira Tanabe
Kenzo Mabe
Akira Tanabe
Kenzo Mabe
Application Number:
JP2014234648A
Publication Date:
January 23, 2019
Filing Date:
November 19, 2014
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C13/00; H01L21/8239; H01L27/105
Domestic Patent References:
| JP201438675A | ||||
| JP2013200922A | ||||
| JP2010182373A | ||||
| JP2004355676A |
Foreign References:
| WO2012132341A1 | ||||
| WO2013080499A1 |
Attorney, Agent or Firm:
Yamato Tsutsui
Atsushi Sugada
Akiko Tsutsui
Tetsuya Sakaji
Atsushi Sugada
Akiko Tsutsui
Tetsuya Sakaji