Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP6998981
Kind Code:
B2
Abstract:
To provide a semiconductor storage device which shortens a period of time for recovery from a deep power-down mode without requiring a dedicated command for terminating the deep power-down mode.SOLUTION: A flash memory 100 includes a standard command I/F circuit 110 and a DPD controller 120 which are operated by an external power source voltage VCC, a voltage supply node INTVDD to which power is supplied from an external power source voltage VCC via a first current route, a voltage supply node INTVDDCP to which power is supplied from the external power source voltage VCC via a second current route, internal circuit groups 140 to 170 connected to the voltage supply node INTVDD, and a charge pump circuit 180 connected to the voltage supply node INTVDDCP. When a DPD mode is terminated, the charge pump circuit 180 is enabled and then the internal circuit groups 140 to 170 are enabled.SELECTED DRAWING: Figure 3
Inventors:
Naoaki Sudo
Application Number:
JP2020035985A
Publication Date:
January 18, 2022
Filing Date:
March 03, 2020
Export Citation:
Assignee:
Winbond Electronics Corporation
International Classes:
G11C5/14; G06F12/00; G11C16/30
Domestic Patent References:
| JP2010055419A | ||||
| JP2007164880A |
Attorney, Agent or Firm:
Kyozo Katayose