PURPOSE: To reduce access time by connecting a sense amplifier for memory cell rewriting to a pair of terminals in a pair of bit lines through a pair of transfer gates.

CONSTITUTION: A pair of the bit lines 1A and 1B connected to the input/output nodes 0A and 0B of the sense amplifier 1 through the transfer gates Q10A and Q10B are connected to the input/output nodes 1AA and 1AB of the sense amplifier for rewriting 1A through the transfer gates Q16A and Q16B. The input/output nodes 1AA and 1AB of the sense amplifier 1A are connected to a pair of bit lines 3A and 3B in a different plate through transfer gates Q36A and Q36B. Thus, a differential signal in the sense amplifier 1 is easily amplified in spite of the capacity of a bit line part, and high speed access is executed.