PURPOSE: To provide the memory cell structure of an SRAM which can materialize stable operation.
CONSTITUTION: A pair of driver transistors 50a and a pair of access transistors 50d are formed on the surface of a silicon substrate 1. A lead wiring layers 13a are made to contact with each of the source/drain regions 5 and 5 of the access transistor through each of the contact holes made in the first insulating layer 11 covering these driver transistor and access transistor. Moreover, a ground wiring layer 13c is made to contact with the source region 5 of the driver transistor through the contact hole made in the first insulating layer 11. This ground wiring layer 13c is made in mesh shape, extending in the column direction and row direction so as to surround the four sides of the lead wiring layer 13a within a memory array, and this is united with the ground wiring layer of each memory cell arranged in the column direction and in the row direction.
ASHIDA MOTOI
YAMAGATA NARIHITO
KOZARU KUNIHIKO
