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Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JPH1074916
Kind Code:
A
Abstract:

To provide a semiconductor storage device wherein, without preventing realing higher density for a memory cell, stable read-out operation is performed to a memory cell array of large variation in threshold after erasing.

In a reading-out operation, when a word line WL (0) is selected with positive selection electric potential (VCC), a source line SL (0) connected to a selected memory cell is taken as a ground electric potential, only a word line WL (1) connected to a selected memory cell and a memory cell sharing a source is taken a negative non-selected electric potential (-VG1), with other word line taken as a ground electric potential, and a source line of a memory cell connected to the other word line is taken as being open. Thereby, supply of negative voltage is only to the word line WL (1), so that as a negative voltage generating circuit it can be of a small scale, thus even when a memory cell having a threshold value of 0V or less at a non-selected memory cell is present, no leak current flows in a bit line, enabling normal reading-out operation.


Inventors:
MORI TOSHIKI
Application Number:
JP23196496A
Publication Date:
March 17, 1998
Filing Date:
September 02, 1996
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
G11C17/00; G11C16/02; G11C16/06; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/115; G11C16/06; H01L21/8247; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Miyai Akio