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Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JPS61142591
Kind Code:
A
Abstract:

PURPOSE: To reduce noise due to the variation of a power supply line by forming the 1st and 2nd sense amplifiers for each pair of bit lines, activating all the 1st sense amplifiers simultaneously by presensing clock and activating only the 2nd sense amplifier corresponding to an address selected by a main sensing clock.

CONSTITUTION: The 1st sense amplifier SA1j and the 2nd sense amplifier SA2j are connected in each pairs of bit lines BLj, BLj'. A MOSFETQ18' for activation to be driven by a presensing clock PSEN is connected to the 2st sense amplifiers SA1j in common. On the other hand, activating MOSFETs Q15' to be driven by respective main sensing clocks MSENj are connected to the 2nd sense amplifiers SA2j respectively. The mutual condactance of the activating MOSFETs Q15' of the 2nd sense amplifiers SA2j for main sensing is larger than that of the activating MOSFETs Q18' of the 1st sense amplifiers SA1j for presensing.


Inventors:
OGURA ISAO
ITO YASUO
Application Number:
JP26330184A
Publication Date:
June 30, 1986
Filing Date:
December 13, 1984
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C7/06; G11C11/409; G11C11/34; G11C11/401; G11C11/4091; (IPC1-7): G11C11/34
Attorney, Agent or Firm:
Takehiko Suzue



 
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