PURPOSE: To reduce the stray capacity of a signal wiring and the interference between data lines and to realize a quick action by arranging a shift register between decoders astride a control signal wiring and transferring data through the decoders.
CONSTITUTION: The shift register is configured with register parts 11W18, 21W28, 31W38 and 41W48, and data lines connected to the registers 11W48 is connected to a corresponding bit line through the decoder 3. A read control signal generator circuit block 61, a shift register control signal generator circuit block 62 and a write control signal generator circuit block 63 generate the signals of control signal lines 51, 52 and 53. With such block constitution the shift registers 11W48 are packed into one, whereby the control lines of the shift registers can use one system in common to substantially reduce the stray capacity of the wiring.
FUJII MASARU
OTA KIYOTO
MAEYAMA YOSHIKAZU
| JPS59198593A | 1984-11-10 | |||
| JPS5698785A | 1981-08-08 |