PURPOSE: To prevent the minority carrier in a substrate from entering into a data line by a method wherein the MISFET of a memory cell is formed by successively superposing a channel region and the second semiconductor region on the first semiconductor region, the first semiconductor region is connected to the electrode of a capacitor, a data line is extended onto a semiconductor substrate and connected to the second semiconductor region.

CONSTITUTION: A memory cell is constituted under each crossing part of the word line WL consisting of a polycrystalline Si film and a data line DL consisting of an Al film, the section between the word line and the data line is insulated by an insulating film 9. Also, the capacitor of the memory cell is composed of the polycrystalline Si film 5 buried in the groove 2 of a substrate 1, the dielectric film 3 such as a silicon oxide film and the like formed between said film 5 and the substrate 1, and the p+ type semiconductor region 4 formed in the vicinity of the dielectric film 3 of the substrate 1. Then, a selective MISFET is constituted on the polycrystalline Si film 5, the MISFET is composed of the gate electrode 8 which is integrally formed by the n+ type semiconductor region 5A and the p- type channel region Ch located on one side of a source and drain and the n+ type semiconductor region 7, a gate insulating film 6 and the word line WL located on the other side of the source and drain. These region 5A, the region Ch and the region 7 are stacked from the lower side successively. As a result, the number of soft errors is reduced, and reading-out and writing-in operations can be performed at high speed.