PURPOSE: To attain high speed readout without malfunction by providing an equalizer between a couple of output nodes of the 1st differential amplifier.
CONSTITUTION: In a dynamic RAM where the bit line sense amplifier consists of a CMOS differential amplifier (1st differential amplifier) 4 as a buffer circuit and a BICMOS differential amplifier (2nd differential amplifier) 5 connected to its output node, an equalizer Q11 is provided to short-circuit outputs nodes of the CMOS amplifier in pairs thereby setting the node in equi-potential when the bit line sense amplifier is not selected. Thus, the output node of the CMOS amplifier is set to equi-potential forcibly in the standby state. Thus, the history of the preceding readout cycle is not left, malfunction is prevented and a highly integrated dynamic RAM capable of high speed readout is obtained.
| JP3498450 | SEMICONDUCTOR STORAGE |
| JPS54150064 | PULSE GENERATION CIRCUIT |
NUMATA KENJI
WATANABE SHIGEYOSHI
