PURPOSE: To improve the productivity of semiconductor storage elements, by switching the type of a high-speed operation mode that is supported with setting of a mode control latch, and therefore realizing different high-speed operation modes including a page mode, a nipple mode, etc. by a common chip.

CONSTITUTION: A 1-bit mode control latch 6 is provided to switch a page mode and a nipple mode each other. When the nipple mode is set at the latch 6, the fetching is inhibited for address inputs A0WA7 together with the refetching to a data latch 3 after the timing T3 fed from a generator 3, and at the fall of a CAS input. At the same time, an address latch 5b can be counted up. The output of the latch 3 is switched by ON and OFF of the CAS input. While the count-up of the latch 5b is inhibited at and after the timing T3 with the output of the latch 6 when a page mode is set. Then it is possible at the fall of the CAS input to refetch the inputs A0WA7 as well as the refetching to the latch 3.