To provide a semiconductor storage of a serial access system in which high speed write-in can be performed by setting forcedly program data to a data latch circuit at the time of a test.

This storage is provided with a memory cell array 14 in which plural memory cells are arranged in a matrix state, a shift register 12 to which write-in data for the memory cell array 14 is transferred and making transferred write-in data correspondent to each column of the memory cell array 14 and outputting it, and a data latch circuit 13 holding write-in data outputted from the shift register 12 and outputting it to each column of the memory cell array 14. At the time of a test, a program data set circuit 15 can write a test pattern to the memory cell array 14 without passing through the shift register 12 by outputting set signals SA0, SA1 making forcedly the data latch circuit 13 a set state to the data latch circuit 13, and a transfer time of a test pattern can be omitted.