To improve an operation speed margin for a row replacement determination process, which arises in a continuous cycle, in a semiconductor storage that comprises a row redundant part replaced by a memory cell row specified by a row address as a redundant part for saving the failure of a built-in memory, and a self-diagnostic circuit used to diagnose the built-in memory.

The semiconductor storage comprises: an address switch detection circuit configured to generate an address detection signal indicating the separation of a replacement determination unit on the basis of the lower bit of the row address; and a failure information holding circuit which holds an entire comparison result signal (comparison result output from a self-diagnostic circuit) until the address detection signal becomes active when not active. A duplication determination process for a replacement row address is allowed to be performed only in the period of time that the address detection signal is active within the replacement determination unit. This makes it possible to spread the duplication determination process of the replacement row address, which arises in a continuous cycle, at replacement determination unit intervals. Accordingly, an operation speed margin for the row replacement determination process can be improved.